Memory Bandwidth vs. Latency Timings

This is an excerpt from a PCStats.com article

When Intel released the i865PE/i875P alongside the Intel Pentium 4C processors, the DDR memory game changed forever. With a DDR memory controller now capable of running dual channel, the Pentium 4 was no longer to be bandwidth limited as it had been with the i845 series. Those single channel DDR chipsets, like the i845PE for instance, could only provide half the bandwidth required by the Pentium 4 processor due to its single channel memory controller.

As the new 800 MHz FSB Pentium 4 processors allowed users to hit never before seen highs in terms of bus speed, many memory manufacturers were trying to capitalize on the situation by releasing every increasing degrees of "high speed" memory.

Unfortunately, to run the memory frequency at the same speed as the FSB (or a 1:1 ratio) almost all the high speed DIMM's (Dual Inline Memory Module) have to have very lax timings. Think about it this way, a car built for drag racing can go dead straight super fast, but cannot maneuver as well as an F1 race car. Likewise, the F1 racer is good in the corners but will be left in the dust on the drag strip. In other words, today's high speed memory modules are built for one thing only, and that's top speed, where timings really aren't considered all that much.